1. Field of the Invention
This invention relates generally to the electronic package. More particularly, this invention relates to a novel packaging configuration with face-to-face-stacked substrate-on-chip module to increase the packing density of electronic devices specially the integrated circuit (IC) memory devices.
2. Description of the Prior Art
There are constant challenges faced by the electronic packaging industry to first increase the packing density. Meanwhile, as the performance level of the integrated circuit is improved, another desired packaging feature is to improve the speed of signal transmission. On the one hand, the extra transmission paths caused by the additional structures imposed by the package often slow the speed of signal transmission down. Additionally, the packaging materials may also generate parasitic capacitance and inductance that will also cause noise and the slowing down of speed of signal transmission. Conventional packaging configurations typically employed with multiple layer of structures as will be illustrated and discussed below are not able to resolve these difficulties.
In U.S. Pat. No. 5,222,014, entitled "Three Dimensional Multi-chip Pad Array Carrier" (issued on Jun. 22, 1993), Lin disclosed a stackable three dimensional multiple chip module. Each level of the chip carrier is interconnected to another level of chip carrier through reflowing of the solder balls. The chip carriers are provided with solder balls on the top and the bottom surfaces of the substrates. FIG. 1A shows the stackable multiple-chip structure. In this packaging structure, the chips are not bare chips but chips that are first packaged by using a first level substrate. are not bare chips but chips that are first packaged by using a first level substrate. Then the packaged chips are mounted on the stackable chip carriers to form a stacking module. Even that improvements are achieved by using a flexibly stackable chip carrier, further improvements of packing density and the signal transmission speed are limited in this kind of pad array carrier stacking configuration. The limitation is inherent because the stacked chips are first packaged in a wire-bonding configuration where all signal paths, i.e., the bonding wires, are routed to bonding pads outside of the die area before stacking. The tacked chip carrier then provides metal traces for transmitting signals between the stacked chips. The speed of the signal transmission is slowed down due to the requirement that the signals have to travel through a longer transmission paths through the bonding wires routed outside of the die area before stacking.
Another prior art structure is shown in FIG. 1B where multiple substrate on chip (SOC) packages are stacked up to increase the packing density. The SOC packages are formed on a lead frame structure. The leads allow for contact on both the top and the bottom surface of the package. The lead framed SOC as shown in FIG. 1B is stacked up as three-dimensional packaging module. The configuration is applied to high density mounting for memory of personal computer (PC) cards. Compared to regular non-stacking configuration, the stacked package as shown in FIG. 2 has a smaller mounting area and occupies less volume. However, the lead frame structure causes the signal to transmitter longer paths from one chip to another chip. Furthermore, a multiple-level configuration commonly implemented in the prior art packaging technology such as this additional layer of lead frame structure imposes additional complexity and limitations. Since all leads from the lead frame are routed to outside of the packaged body along the perimeters, it imposes a limitation on the minimum body size for a given lead pitch. Furthermore, the additional processing steps of lead wrapping and lead stacking will impact the cost and yield of manufacturing.
Therefore, a need still exits in the art to provide an improved configuration and procedure for increasing the packing density and to prevent signal transmission delays caused by structures added by the packaging structures.